ESD protection for FinFETs is challenging!

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ESD protection for FinFETs is challenging. There are 3 main ESD issues for FinFET chips.
(1) FinFET circuits are sensitive. There is a drastic reduction in failure voltage for transistor gates and junctions compared to 28nm CMOS
(2) Traditional or conventional ESD approaches are not good enough for advanced FinFET applications. Snapback NMOS based concepts are not effective anymore. Rail-based protection introduces a lot of leakage and cannot be used for the most sensitive interfaces
(3) SoCs designed in FinFET technology are complex. The number of design rules increases with every node and custom layout is further restricted. The design time increases with 2x to 4x according to several sources. This complexity also plays a role in the selection of the optimal ESD protection solutions

Fortunately, Sofics has silicon and product proven ESD-IP for the major FinFET processes.
Sofics ESD solutions have additional benefits like drastically lower leakage and can enable high-speed applications and interfaces with higher voltage tolerance.

Get more information on ESD protection for FinFETs on Sofics website: sofics.com/index.php?view=sofics-finfet
Contact Sofics or read more on our website: sofics.com

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